Title: Designing High Speed 64 bit Multiplier using Vedic Sutra


Volume 10 Issue 1 Year 2020

Authors:

Pragya Pandey

pandeypragya1107@gmail.com
Department of Electronics and Communication, Geetanjali Institute of Technical Studies, Udaipur- 313004 (INDIA),

Latif Khan

latifnizami@gmail.com
1Department of Electronics and Communication, Geetanjali Institute of Technical Studies, Udaipur- 313004 (INDIA),

C.P. Jain

cpjain@eceajmer.ac.in
Department of Electronics and Communication, Govt.Engineering College, Ajmer-305002 (INDIA)

Pages: 31-35


Abstract:

Vedic multiplier is a unique and prompt multiplier dependent on Vedic mathematics. The main component used in this procedure is adder. Vedic multiplier’s performance can be enhanced by using fast adder.  Hence in this paper we are using 64*64 bit multiplier using 32-bit Vedic multiplier and getting path delay lowest. For finding value of 64-bit multiplier, we need 32-bit  multiplier for multiplication. Here we are applying Vedic Mathematics Sutra called “URDHVA TIRYAKABHYAM” for proposed 64*64 bit multiplier in Xilinx ISE 14.7. This design does not take more time for execution of the operation than comparison with available multiplier. This Vedic method is effective to improve the speed of image processing and digital signal processing. It works on high speed with great performance. This technique includes different types of wide area of image and digital signal processing. At the end, the result of proffered multiplier is compared with 64-bit multiplier using different adders.

Keywords:
Ancient Vedic mathematics, Urdhva-Tiryakbhyam Sutra, Vedic real multiplier, Kogge- Stone Adder (KSA), Xilinx ISE 14.7, VHDL