Carbon Nanotube Field Effect Transistor (CNFET) is known for high performance, stability and low power consumption it is potential candidate to replace silicon in the future. Therefore SRAM Cell design based on CNFET is widely used as low power, highly stable and less delay memory. This paper proposes a new 7T SRAM cell based on CNFET that reduces delay and power consumption during write operation. Read delay and static noise margin are improved by careful cell transistors sizing. In this paper, CNFET based 7T SRAM Cell is designed and its performance analyzed at Vdd 1.8V and 0.9V. HSPICE simulations of the 7T SRAM cell using Stanford CNFET model at 0.9V using 32nm propagation technology shows that power dissipation is reduced by 10.95%, delay is reduced by 0.14%, noise margin at high level is increased by 14.5% and at low level 11.13% , and PDP is reduced by 11.05% in comparison to 7T SRAM Cell at 1.8V.
CNFET, SRAM, HSPICE, Low power, Power Dissipation