Title: High level synthesis of L-bubble check algorithm for check node processing


Volume 10 Issue 1 Year 2020

Authors:

Himanshu Sharma

sharmahimanshu290493@gmail.com
Department of Electronics and Communication, Swami Keshvanand Institute of Technology, Management and Gramothan, Jaipur-302017 (INDIA),

Manju Choudhary

ijskit@skit.ac.in
Department of Electronics and Communication, Swami Keshvanand Institute of Technology, Management and Gramothan, Jaipur-302017 (INDIA),

Vikas Pathak

ijskit@skit.ac.in
Department of Electronics and Communication, Swami Keshvanand Institute of Technology, Management and Gramothan, Jaipur-302017 (INDIA),

Ila Roy Saxena

illaroy611@gmail.com
Department of Electronics and Communication, Swami Keshvanand Institute of Technology, Management and Gramothan, Jaipur-302017 (INDIA)

Pages: 26-30


Abstract:

This paper deals with the low complexity algorithm for the check node processing i.e. L-bubble check algorithm in non-binary LDPC decoders. After a review of the state-of-the-art, there is a focus on a reduction of hardware requirement for check node processing using high level synthesis. High level synthesis helps in optimizing the hardware design to a great extent. This motivated to use high level synthesis for implementing the L-bubble check algorithm. Finally, high level synthesis results are presented which shows that the number of slices required to implement the L-bubble check algorithm using HLS is 204.

Keywords: