Title: Hardware Implementation of Single Precision Floating Point Arithmetic Unit


Authors:

Noorjabeen

noorkhan984914@gmail.com
Department of Electronics & Communication Engineering, Swami Keshvanand Institute of Technology, Management and Gramothan, Jaipur, India,

Vikas Pathak

vikas.pathak@skit.ac.in
Department of Electronics & Communication Engineering, Swami Keshvanand Institute of Technology, Management and Gramothan, Jaipur, India,

Rahul Vijay

vijay.rahul1986@gmail.com
Department of Electronics & Communication Engineering, Banasthali Vidyapith, Jaipur, India

Pages: 40-45

DOI:

Abstract:

This research paper represents the floating point arithmetic calculations. In this work floating point arithmetic unit multiplication and addition have been performed. In this manuscript, IEEE 754 standard of 32 bit single precision floating point arithmetic is used.  Floating-point arithmetic is useful for high dynamic range arithmetic, but is more resource intensive than integer arithmetic. Floating point calculations occur on system has a wide range of values that require fast processing times. This research paper represents the redesign of floating point arithmetic unit. It deals with the ALU similar structure which performs addition / subtraction and multiplication with the selection line. If the selection line  is ‘1’ then it performs addition/ subtraction otherwise for selection line ‘0’ multiplication of floating point numbers is done.  The proposed design is simulated using Xilinx Isim Simulator and synthesized and impleneted using Xilinx ISE on Nexys – 4 DDR FPGA device.

Keywords:
ALU, FPGA, Single precision, hardware implementation, Floating point Arithmetic