Abstract:
In this manuscript, the VLSI implementation of the arithmetic unit of the floating point number algorithm is executed. Due to this operation, it has been optimized for adder, subtractor, and multiplier. The execution of this module can be utilized by the MAC unit. MAC Unit is further used in other applications like IIR & FIR filters. This arithmetic unit is based on a floating point standard format named as “IEEE 754”. Floating point numbers are used to represent the real numbers with point values. The linear convolution technique uses a series of addition and multiplication operations. Therefore, it is regarded as the essential building block of an FIR and IIR filters using a multiplier unit. Both multiplication and accumulation operations are carried out by the MAC unit. The Arithmetic Logic Unit (ALU), which executes arithmetic and logical operations, is the essential building block for arithmetic processors. This floating point arithmetic unit can also be used for the ALU of processor. The proposed hardware arithmetic unit is implemented on Nexys – 4 DDR (Artix – 7 FPGA family) trainer kit using VHDL language. Xilinx ISE 2014.4 EDA software is used for synthesis and simulation of the proposed design.
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