Title: Design and Simulation of IIR Anti-Notch Filter for Frequency Suppression Applications


Authors:

Vikas Pathak

vikas.pathak@skit.ac.in
Department of Electronics & Communication Engineering, Swami Keshvanand Institute of Technology, Management & Gramothan, Jaipur-302017 (INDIA),

Neeraj Jain

neeraj.jain@skit.ac.in
Department of Electronics & Communication Engineering, Swami Keshvanand Institute of Technology, Management & Gramothan, Jaipur-302017 (INDIA),

Abhinandan Jain

abhinandan.jan@skit.ac.in
Department of Electronics & Communication Engineering, Swami Keshvanand Institute of Technology, Management & Gramothan, Jaipur-302017 (INDIA),

Harshal Nigam

harshal.nigam@skit.ac.in
Department of Electronics & Communication Engineering, Swami Keshvanand Institute of Technology, Management & Gramothan, Jaipur-302017 (INDIA)

Pages: 46-50

DOI:

Abstract:

Digital filters have become an integral part of modern signal processing systems, enabling the selective modification or suppression of specific frequency components. This paper presents the design and simulation of a second-order Infinite Impulse Response (IIR) Anti-Notch filter aimed at attenuating unwanted narrowband frequency components from digital signals. The Anti-Notch filter, also known as a notch-reject or notch-suppression filter, effectively eliminates disturbances such as power-line hum or interference from communication channels. The filter was designed using MATLAB, focusing on key parameters such as pole radius, notch frequency, and sampling rate. Simulation results show a distinct frequency attenuation at the targeted frequency while maintaining minimal distortion in the passband. Compared to FIR designs, the proposed IIR Anti-Notch filter achieves a compact structure, low computational complexity, and reduced delay, making it highly suitable for real-time audio and communication applications. The design was further implemented on an FPGA platform using Xilinx ISE to validate its real-time performance. The hardware and MATLAB results show complete suppression of the 300 Hz component from a composite input signal containing 100 Hz, 300 Hz, and 700 Hz frequencies, verifying the filter’s accuracy and timing efficiency. The optimized second-order structure minimizes hardware utilization while ensuring numerical stability and high signal fidelity, demonstrating its practical effectiveness in embedded and high-speed digital signal processing systems. The designed IIR Anti-Notch filter achieves approximately 50.2 dB attenuation at the rejection frequency of 300 Hz, with less than 0.5 dB passband ripple and a −3 dB bandwidth of 12 Hz. The FPGA implementation operates at a maximum frequency of 34.25 MHz, confirming real-time feasibility.

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